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Dr. Amir-Mohammad Rahmani-Sane

Date of doctoral defense: 14.12.2012

TUCS Department for the doctoral studies: University of Turku, Department of Information Technology

Admitted to TUCS GP on 15.9.2009

Graduate project title:

Exploration and Design of Power-Efficient Networked Many-Core Systems

Graduate project abstract:

Multiprocessing is a promising solution to meet the requirements of near future applications. To get full benefit from parallel processing, a many-core system needs efficient, on-chip communication architecture. Network-on-Chip (NoC) is a general purpose communication concept that offers high-throughput, reduced power consumption, and keeps complexity in check by a regular composition of basic building blocks. This thesis presents power efficient communication approaches for networked many-core systems. We address a range of issues being important for designing power-efficient many-core systems at two different levels: the network-level and the router-level.

From the network-level point of view, exploiting state-of-the-art concepts such as Globally Asynchronous Locally Synchronous (GALS), Voltage/Frequency Island (VFI), and 3D Networks-on-Chip approaches may be a solution to the excessive power consumption demanded by today's and future many-core systems. To this end, a low-cost 3D NoC architecture, based on high-speed GALS-based vertical channels, is proposed to mitigate high peak temperatures, power densities, and area footprints of vertical interconnects in 3D ICs. To further exploit the beneficial feature of a negligible inter-layer distance of 3D ICs, we propose a novel hybridization scheme for inter-layer communication. In addition, an efficient adaptive routing algorithm is presented which enables congestion-aware and reliable communication for the hybridized NoC architecture. An integrated monitoring and management platform on top of this architecture is also developed in order to implement more scalable power optimizatio
n techniques.

From the router-level perspective, four design styles for implementing power-efficient reconfigurable interfaces in VFI-based NoC systems are proposed. To enhance the utilization of virtual channel buffers and to manage their power consumption, a partial virtual channel sharing method for NoC routers is devised and implemented.

Extensive experiments with synthetic and real benchmarks show significant power savings and mitigated hotspots with similar performance compared to latest NoC architectures. The thesis concludes that careful co-designed elements from different network levels enable considerable power savings for many-core systems.

Former supervisors:

Pasi Liljeberg (University of Turku, Department of Information Technology)

Juha Plosila (University of Turku, Department of Information Technology)

Hannu Tenhunen (University of Turku, Department of Information Technology)

Latest publications:

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